1. Field of the Invention
The present invention relates to the field of electronic circuits. More particularly, the present invention relates to a circuit for accurately calculating address information with minimal delay.
2. Description of the Prior Art
It is fundamental to the operations of microprocessors and those electronic devices incorporating microprocessor(s) to support digital (i.e., binary) addition of at least two digital inputs. Normally, microprocessors employ integrated circuits which perform various arithmetic or logical ("bitwise") operations on multiple digital inputs for calculating digital sums and other logical functions. For example, an address generation unit ("AGU") is employed within the microprocessor in order to calculate an Effective Address ("EFF.sub.-- ADDR"), which is used for checking the memory address offset for addressing violations and a Linear Address ("LIN.sub.-- ADDR") for accessing virtual memory locations. Both the Effective and Linear Addresses are calculated according to the following equations by using a combination of carry-save adders ("CSAs") and carry propagate adders ("CPAs") in parallel to "add" certain digital inputs; namely, a base address ("S1"), an index multiplied by any scaling factor ("S2"), a displacement ("S3") and subsequently, a segment base ("S4"). EQU EFF.sub.-- ADDR=S1+S2+S3; and Eqn. 1 EQU LIN.sub.-- ADDR=EFF.sub.-- ADDR+S4, where Eqn. 2
"+" is an operator representing a normal arithmetic addition.
Referring to FIG. 1, an conventional architecture of addressing circuitry 100 of the AGU, implemented within conventional x86 Intel.RTM. Microprocessor Architecture, is shown. The addressing circuitry 100 is capable of producing the Effective and Linear Addresses to support a selected addressing mode. More specifically, the addressing circuitry 100 may be configured to operate in a 16-bit addressing mode in order to support older addressing architectures and application programs relying on 16-bit addressing. This occurs when the S1, S2 and S3 inputs are 16-bits in length. However, the addressing circuitry 100 also may be configured to operate in a 32-bit addressing mode to support current application programs relying on 32-bit addressing.
In order to correctly calculate the Linear Address, the conventional addressing circuit 100 first calculates the Effective Address by inputting digital inputs S1, S2 and S3 via 32-bit-wide communication lines 105-107 into a 3:2 carry-save adder ("3:2 CSA") 110. The 3:2 CSA 110 produces sum signals for calculating the Effective Address, namely E.sub.-- SUM.sub.0, E.sub.-- SUM.sub.1 through E.sub.-- SUM.sub.31 (collectively referred to as "E.sub.-- SUM.sub.31-0 " signals) via communication lines 115. These E.sub.-- SUM.sub.31-0 signals are bitwise sums produced by adding corresponding bits of the S1, S2 and S3 inputs. In addition, the 3:2 CSA 110 produces carry signals, i.e., E.sub.-- CARRY.sub.0 -E.sub.-- CARRY.sub.31, corresponding to E.sub.-- SUM.sub.0 -E.sub.-- SUM.sub.31, which are collectively referred to as "E.sub.-- CARRY.sub.31-0 " signals, via communication lines 116.
The E.sub.-- SUM.sub.31-0 and E.sub.-- CARRY.sub.31-0 signals are input into a conventional adder 120 (e.g., a carry propagate adder, carry ripple adder, carry look-ahead adder, Kogge-Stone adder and the like) which calculates the Effective Address. The Effective Address is transferred through communication lines 121 which are separately routed to different components. As shown, sixteen (16) communication lines 122 associated with the least significant 16-bits of the Effective Address (hereinafter referred to as "EA[15:0]") are coupled directly to a second conventional adder 130 while sixteen (16) communication lines 123 associated with the most significant sixteen (16) bits of the Effective Address (hereinafter referred to as "EA[31:16]") are routed to a masking logic unit 125.
The masking logic unit 125 is combinatorial logic (not shown), for example, sixteen logic gates with AND gate functionality configured in parallel so that one input of each logic gate is coupled to different communication lines 123 and the other input to a common, active-low MASK line 126. If the addressing circuitry 100 is operating in 16-bit addressing mode, the MASK line 126 is asserted based on control signals resulting from the operation being performed. This causes EA[31:16] to be "masked" (i.e., sets each of these bits to logic level "0" according to standard TTL logic) before being output to the second conventional adder 130 via communication lines 127. Such masking is done to ensure that no carries are generated or propagated from the addition of S1, S2 and S3 inputs which would effect the value of t Linear Address. However, in 32-bit addressing mode, the MASK line 126 is deasserted so that the true bit representation of EA[31:16] is output to the second conventional adder 130.
In either of the above cases, the masking logic unit 125 outputs a selectively masked sum representing EA[31:16], in synchronism with EA[15:0], into the second conventional adder 130. The second conventional adder 130 receives the S4 input, typically a 32-bit address segment base, via communication lines 131 and calculates the Linear Address therefrom in accordance with Eqn. 2 listed above.
Clearly, this conventional addressing scheme requires a three step process for calculating the Linear Address for 16-bit addressing; namely, (i) calculating the Effective Address; (ii) selectively masking EA[31:16] if operating in 16-bit addressing mode; and (iii) adding the Effective Address or alternatively EA[15:0] and the masked EA[31:16] with the segment base. As a result, these sequential steps ensure that no carries are generated from the Effective Address by clearing those bits associated with EA[31:16]. Such carries could effect the calculated value of the Linear Address. However, as operational speed of the processor increases, this architecture for serially calculating Effective and Linear Addresses fails to meet necessary timing constraints.
Thus, it would be advantageous to calculate both the Effective and Linear Addresses in parallel while still supporting 16 or 32-bit addressing. As a result, parallel calculations would have significant impact on the overall performance of the processor.